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* version 2 for more details (a copy is included in the LICENSE file that
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* 2 along with this work; if not, write to the Free Software Foundation,
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#ifndef CPU_SPARC_DISASSEMBLER_SPARC_HPP
#define CPU_SPARC_DISASSEMBLER_SPARC_HPP
static int pd_instruction_alignment() {
return sizeof(int);
}
static const char* pd_cpu_opts() {
return "v9only";
}
// Returns address of n-th instruction preceding addr,
// NULL if no preceding instruction can be found.
// With SPARC being a RISC architecture, this always is BytesPerInstWord
// It might be beneficial to check "is_readable" as we do on ppc and s390.
static address find_prev_instr(address addr, int n_instr) {
return addr - BytesPerInstWord*n_instr;
}
// special-case instruction decoding.
// There may be cases where the binutils disassembler doesn't do
// the perfect job. In those cases, decode_instruction0 may kick in
// and do it right.
// If nothing had to be done, just return "here", otherwise return "here + instr_len(here)"
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