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#ifndef CPU_SPARC_C1_LIRASSEMBLER_SPARC_HPP
#define CPU_SPARC_C1_LIRASSEMBLER_SPARC_HPP
private:
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// Sparc load/store emission
//
// The sparc ld/st instructions cannot accomodate displacements > 13 bits long.
// The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode
// by allowing 32 bit displacements:
//
// When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]).
// When disp > 13 bits long, code is emitted to set the displacement into the O7 register,
// and then a load or store is emitted with ([O7] + [d]).
//
int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned);
int store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide);
int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned);
int load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide);
void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no);
int shift_amount(BasicType t);
static bool is_single_instruction(LIR_Op* op);
// Record the type of the receiver in ReceiverTypeData
void type_profile_helper(Register mdo, int mdo_offset_bias,
ciMethodData *md, ciProfileData *data,
Register recv, Register tmp1, Label* update_done);
// Setup pointers to MDO, MDO slot, also compute offset bias to access the slot.
void setup_md_access(ciMethod* method, int bci,
ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias);
enum {
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